(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a thin film capacitor having a metal-insulator-metal (MIM) structure.
(b) Description of the Related Art
Recently, in the field of high-speed analog circuitry, semiconductor devices for making a capacitor with high capacitance have been under development. Generally, when a capacitor has a PIP structure (where a polysilicon layer, an insulator layer, and a polysilicon layer are deposited), there is a disadvantage that, as the upper electrode and the lower electrode use conductive polysilicon, a natural oxide may be formed by oxidation at the interfaces between the electrodes and a dielectric thin film. Thus, total capacitance of the PIP device may be reduced.
To overcome this disadvantage, the structure of a capacitor has been changed to a metal-insulator-silicon (MIS) structure or a metal-insulator-metal (MIM) structure. Since an MIM capacitor has relatively low resistivity and no inner parasitic capacitance due to depletion therein, it is mainly used in high performance semiconductor devices.
FIG. 1 is a sectional view of a conventional thin film capacitor having an MIM structure. As shown in FIG. 1, this conventional thin film capacitor has a lower electrode 3 formed on a lower insulating layer 2 which is formed on a semiconductor substrate 1. In addition, an anti-reflective coating 4 is formed on the lower electrode 3, and a dielectric layer 5 and upper electrode 6 are sequentially formed on the anti-reflective coating 4. Here, the lower electrode 3 corresponds to a first electrode layer of the MIM capacitor, and the upper electrode 6 corresponds to a second electrode layer thereof.
In such a conventional MIM capacitor, the capacitance thereof depends in significant part on, e.g., an area of the upper electrode 6. Accordingly, to achieve high capacitance of an MIM device, the area of the electrode should be increased. However, in this case, it is difficult to achieve a highly integrated device (e.g., increasing the area of the MIM device reduces the number of devices per unit area).
In addition, manufacturing such an MIM device may be problematic. For example, a short circuit may be caused when the dielectric layer 5 is etched. In some cases, the lower electrode 3 may be etched together with the dielectric layer 5 and then re-deposited to sidewalls of the dielectric layer 5 and the upper electrode 6 ( phenomenon sometimes known as “back sputtering”).
In addition, the capacitor characteristics may be deteriorated due to fringe (or parasitic) capacitance at the sidewalls of a conventional MIM capacitor, particularly as the height-to-width ration of the electrodes in such capacitors increases.
The information disclosed in this Background of the Invention section is only for enhancement of understanding of the background of the invention and therefore, unless explicitly described to the contrary, it should not be taken as an acknowledgement or any form of suggestion that this information forms prior art that is already known in this country to a person of ordinary skill in the art.